1. Field
The present invention relates to a stacked wafer level package and a method of manufacturing the same, and more particularly, to a stacked wafer level package and a method of manufacturing the same capable of improving a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer.
2. Description of the Related Art
These days, the electronics industry has a tendency to manufacture products with light weight, small size, high speed, multiple functions, high performance and high reliability at low cost. A semiconductor package is one of important technologies to achieve the above-described objects in designing the products.
Since the semiconductor package, which is a technology to efficiently package devices used in electronic products, is important enough to affect performance of a semiconductor device and cost, performance and reliability of a final product, it has been developed in various forms.
A stacked chip package, one of the semiconductor packages, has an advantage of increasing capacity of the semiconductor package or minimizing a mounting area based on the capacity of the semiconductor package by stacking semiconductor chips to manufacture a single package.
A manufacturing method of the stacked chip package includes both a wafer fabrication process of manufacturing individual semiconductor chips and a package assembly process of separating the individual semiconductor chips from a wafer to assemble a semiconductor package as a final product.
Like this, since the conventional method of manufacturing the stacked chip package includes both the wafer fabrication process and the package assembly process, it causes increase in throughput until completing the final product and deterioration of reliability and increase in process costs due to complication of processes. Therefore, finally, since the product is manufactured at high cost, there are disadvantages such as deterioration of price competiveness and so on.
Accordingly, a stacked wafer level package, which is manufactured by including processes of forming a rearrangement wiring layer, stacking a dielectric layer and forming a via hole on a chip after mounting the chip on a substrate, is developed. That is, the stacked wafer level package can reduce manufacturing process, time and cost by performing both manufacture and packaging of the semiconductor chip on the wafer substrate.
However, in the stacked wafer level package, a contact failure between the chip and the rearrangement wiring layer, which is formed in the following process, can be caused by a difference of thermal expansion coefficient between the wafer substrate and the semiconductor chip or deformation of the wafer substrate such as deflection, which is generated by a thermal treatment process performed after mounting the chip. Also, many failures can be caused in the following processes performed after mounting the chip, for example, a layer stacking process, a via hole forming process and so on.
In addition, misalignment of the stacked chip can be caused by the deformation of the wafer substrate in a process of further stacking another chip on the chip.
Therefore, the conventional stacked wafer level package technology capable of reducing manufacturing process and time has been developed but so far there have been problems such as reduction of yield and increase in cost due to misalignment generated in a stacking process.